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Digital-to-analog converter (DAC)
RM0008
12.5.14
Table 70.
DAC register map
The following table summarizes the DAC registers.
DAC register map
Offset
Register
0x00
DAC_CR
Reserved
MAMP2[3:0]
WAVE
2[2:0]
TSEL2[2:0]
Reserved
MAMP1[3:0]
WAVE
1[2:0]
TSEL1
[2:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DAC_SWTRIG
0x04
R
Reserved
Reset value
0
0
0x08
DAC_DHR12R
1
Reserved
DACC1DHR[11:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0x0C
DAC_DHR12L
1
Reserved
DACC1DHR[11:0]
Reserved
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0x10
DAC_DHR8R1
Reset value
Reserved
0
0
DACC1DHR[7:0]
0 0 0 0
0
0
0x14
DAC_DHR12R
2
Reserved
DACC2DHR[11:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0x18
DAC_DHR12L
2
Reserved
DACC2DHR[11:0]
Reserved
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0x1C
DAC_DHR8R2
Reserved
DACC2DHR[7:0]
0x20
DAC_DHR12R
D
Reserved
DACC2DHR[11:0]
Reserved
DACC1DHR[11:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x24
DAC_DHR12L
D
DACC2DHR[11:0]
Reserved
DACC1DHR[11:0]
Reserved
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x28
DAC_DHR8RD
Reset value
Reserved
0
0
DACC2DHR[7:0]
0 0 0 0
0
0
0
0
DACC1DHR[7:0]
0 0 0 0
0
0
0x2C
0x30
DAC_DOR1
Reset value
DAC_DOR2
Reset value
Reserved
Reserved
0
0
0
0
0
0
DACC1DOR[11:0]
0 0 0 0 0
DACC2DOR[11:0]
0 0 0 0 0
0
0
0
0
0
0
0
0
Note:
252/995
Refer to Table 1 on page 41 for the register boundary addresses.
Doc ID 13902 Rev 9
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